1. Field of the Invention
The present invention relates to a structure and method for approximating an analog signal with a digital signal. In particular, the present invention relates to an analog to digital converter for use in a digital integrated circuit.
2. Description of the Prior Art
Certain integrated circuits are fabricated to include only digital circuitry. These integrated circuits are referred to as digital integrated circuits. Examples of digital integrated circuits include field programmable gate arrays (FPGAs) and programmable logic arrays (PLAs). It is more expensive to fabricate analog circuit elements on a digital integrated circuit. Therefore, when an analog circuit must be used in conjunction with a digital integrated circuit, the analog circuitry is sometimes fabricated on a separate chip using a separate process. This increases the cost and size of a system which utilizes both the digital integrated circuit and the analog circuitry.
An analog-to-digital converter (ADC) is a hybrid circuit which includes both analog and digital circuitry. Such ADCs are sometimes used in connection with an FPGA. FPGAs are standard programmable integrated circuits which include predetermined resources, each able to perform many functions in response to a user command. However, ADC's are not available as one of these functions. As previously discussed, forming the analog circuitry of the ADC on the FPGA would be inconvenient and expensive. Consequently, prior art ADCs used in connection with FPGAs are typically fabricated on a separate chip.
FIG. 1 is a schematic diagram of a prior art ADC 1. ADC 1 includes counter 2, digital-to-analog converter (DAC) 3, analog comparator 4 and register 5. Counter 2 counts up from a minimum count to a maximum count and then resets and repeats the count. DAC 3 receives the count of counter 2 and in response generates an analog ramp signal which is representative of this count. Analog comparator 4 compares the analog ramp signal with the input signal (V.sub.IN). When the analog ramp signal becomes greater than input signal V.sub.IN, analog comparator 4 provides a signal which enables register 5 to receive the current count of counter 2. This current count is provided as a digital output signal (V.sub.OUT) on bus 6.
Analog comparator 4 is an analog circuit. Thus, when utilizing ADC 1 in connection with an FPGA, analog comparator 4 is typically fabricated on a separate chip. As a result, the cost of the system utilizing the digital integrated circuit is increased.
It is therefore desirable to have an ADC which does not require an analog comparator. It is also desirable to have an ADC which is capable of being fabricated with a significant number of elements on a digital integrated circuit chip and a minimum number of external elements.